//testbench
`timescale  1ns / 1ps

module testbench_demo;

parameter PERIOD  = 10;

//输入
reg clk=0;
reg rst_n=0;
reg [3:0] i_data;
reg [3:0] q_data;
reg ready_in=0;
reg [1:0] sel=0;

//输出
wire [4:0] out_data;
wire ready_out;

//生成时钟
initial
begin
    forever #(PERIOD/2)  clk=~clk;  //每隔5ns，时钟取一次反
end

//生成输入
initial
begin
    #(PERIOD*2) rst_n = 1;
    #200
    i_data = 4'd5;
    q_data = 4'ha;
    #100
    ready_in = 1;
    sel = 2'b10;
end

//例化
demo u_demo(
    .clk(clk),
    .rst_n(rst_n),
    .i_data(i_data),
    .q_data(q_data),
    .ready_in(ready_in),
    .sel(sel),
    .out_data(out_data),
    .ready_out(ready_out)
);

endmodule